The present invention relates to booster circuits for use in semiconductor integrated circuit devices such as nonvolatile semiconductor memories.
A booster circuit that compares an increased output potential (boosted potential) with a reference potential to control the upper limit of the boosted potential has been conventionally used to prevent the breakdown of a transistor provided to determine the upper limit of the boosted potential in a high-voltage supplying circuit for erasing and writing in a nonvolatile semiconductor memory, for example, (e.g., in Japanese Laid-Open Publication No. 4-132088).
FIG. 20 shows an example of a configuration of a conventional booster circuit disclosed in the above publication.
As shown in FIG. 20, each of n pumping circuits 811 through 81n (where n is an integer of one or more) includes: first and second nMOS transistors MN1 and MN2 which are connected in series and each of which has its gate and drain connected to each other; and first and second pumping capacitances C1 and C2 whose electrodes at one side are connected to the gates of the respective transistors MN1 and MN2 and whose electrodes at the other side receive pumping control signals Tc and Bc which are complementary signals output from a pumping control signal generator 860.
The pumping circuit 811 at the initial stage is connected to a power supply terminal Vcc in a forward direction via a power supply transistor NTr81 made of an nMOS transistor whose gate and drain are connected. The output terminal of the pumping circuit 81n at the final stage is connected to the source of a pull-up nMOS transistor NTr82 whose gate and drain are connected to a power supply terminal Vcc to allow a boosted potential (output potential) VPUMP to be taken out. The output terminal of the pumping circuit 81n is also connected to an input terminal of a boosted potential sensor 820.
The boosted potential sensor 820 receives the boosted potential VPUMP at its input terminal and outputs a comparison output potential VPUMPC from its output terminal to a non-inverted input terminal of a comparison amplifier 830.
The comparison amplifier 830 is a differential amplifier which receives a reference potential VREF from a reference potential generator 840 at its non-inverted input terminal, compares the comparison output potential VPUMPC from the boosted potential sensor 820 with the reference potential VREF from the reference potential generator 840, and outputs the comparison result to the pumping control signal generator 860.
Hereinafter, it will be described how the booster circuit having the aforementioned configuration operates.
The booster circuit shown in FIG. 20 drives the potentials of the first and second pumping capacitances C1 and C2 constituting each of the pumping circuits 811 through 81n at high and low levels each in alternation with the other using the complementary clock signals Tc and Bc generated by the pumping control signal generator 860. Accordingly, a potential (VCC−VTH+ΔV) obtained by adding a boosted potential difference ΔV determined by the number n of stages to a potential (VCC−VTH) supplied via the power supply transistor NTr81 having a threshold voltage VTH is obtained as the output potential VPUMP of the booster circuit.
The comparison amplifier 830 continues boosting operation during a period in which the reference potential VREF is higher than or equal to the comparison output potential VPUMPC, i.e., VREF≧VPUMPC, while stopping the boosting operation during a period in which the reference potential VREF is lower than the comparison output potential VPUMPC, i.e., VREF<VPUMPC.
As another conventional example, a technique of controlling the output potential by making the pulse width of a pumping pulse variable depending on the value of the output potential (boosted potential) has been proposed.
However, in the booster circuit shown in FIG. 20, overshoot or undershoot occurs in the output potential with respect to a given boosted potential, i.e., a target value, as shown in FIG. 21, so that it is difficult to control the boosted output potential. This is because the booster circuit is switched between boosting operation and boosting suspension in accordance with the output potential, so that a sense delay and other factors cause a delay in determining the output potential.
The conventional boosting technique for controlling the pumping pulse width has another problem of large circuit scale and a large amount of power consumption in a control circuit for controlling the pulse width. This problem arises because the pulse-width control circuit controls the pulse width by generating an intermediate potential in accordance with the output value of the boosted potential and inputting the intermediate potential to a pulse generator.